Tài liệu DSP Builder Reference Manual ppt

Contents v
© March 2009 Altera Corporation DSP Builder Reference Manual
Chapter 7. Rate Change Library
Multi-Rate DFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3
Tsamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
Chapter 8. Simulation Library
External RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1
Multiple Port External RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3
Chapter 9. Storage Library
Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2
Down Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–3
Dual-Clock FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–4
Dual-Port RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–7
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10
LUT (Look-Up Table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–11
Memory Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–13
Parallel To Serial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–14
ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–16
Serial To Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–18
Shift Taps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–20
Single-Port RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–21
True Dual-Port RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–24
Up Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–28
Chapter 10. State Machine Functions Library
State Machine Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1
State Machine Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–3
Chapter 11. Boards Library
Board Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1
Cyclone II DE2 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2
Cyclone II EP2C35 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–4
Cyclone II EP2C70 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–5
Cyclone III EP3C25 Starter Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–7
Cyclone III EP3C120 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–8
Stratix EP1S25 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–12
Stratix EP1S80 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–14
Stratix II EP2S60 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–15
Stratix II EP2S180 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–17
Stratix II EP2S90GX PCI Express Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–18
Stratix III EP3SL150 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–20
Appendix A. Example Designs
Tutorial Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3
Amplitude Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3
HIL Frequency Sweep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4
Switch Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4
Avalon-MM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4
Avalon-MM FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4
HDL Import . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–5
Subsystem Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–5
Custom Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–5
vi Contents
DSP Builder Reference Manual © March 2009 Altera Corporation
State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–5
Demonstration Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–5
CIC Interpolation (3 Stages x75) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–5
CIC Decimation (3 Stages x75) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–6
Convolution Interleaver Deinterleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–6
IIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–6
32 Tap Serial FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–6
MAC based 32 Tap FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–7
Color Space Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–7
Farrow Based Resampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–7
CORDIC, 20 bits Rotation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–8
Imaging Edge Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–8
Quartus II Assignment Setting Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–8
SignalTap II Filtering Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–8
SignalTap II Filtering Lab with DAC to ADC Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–8
Cyclone II DE2 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–9
Cyclone II EP2C35 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–9
Cyclone II EP2C70 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–9
Cyclone III EP3C25 Starter Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–9
Cyclone III EP3C120 DSP Board (LED/PB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–9
Cyclone III EP3C120 DSP Board (7-Seg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–9
Cyclone III EP3C120 DSP Board (HSMC A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–10
Cyclone III EP3C120 DSP Board (HSMC B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–10
Stratix EP1S25 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–10
Stratix EP1S80 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–10
Stratix II EP2S60 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–10
Stratix II EP2S180 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–11
Stratix II EP2S90GX PCI Express Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–11
Stratix III EP3SL150 DSP Board (LED/PB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–11
Stratix III EP3SL150 DSP Board (7-Seg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–11
Stratix III EP3SL150 DSP Board (HSMC A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–11
Stratix III EP3SL150 DSP Board (HSMC B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–12
Combined Blockset Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–12
Appendix B. Categorized Block List
AltLab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1
Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1
Complex Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–2
Gate & Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–2
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–3
IO & Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–3
Rate Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–4
Simulation Blocks Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–4
State Machine Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–4
Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–4
Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–5
Additional Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2
Alphabetical Index
© March 2009 Altera Corporation DSP Builder Reference Manual
1. AltLab Library
The blocks in the AltLab library are used to manage design hierarchy and generate
RTL VHDL for synthesis and simulation.
The AltLab library contains the following blocks:
■ BP (Bus Probe)
■ Clock
■ Clock_Derived
■ Display Pipeline Depth
■ HDL Entity
■ HDL Import
■ HDL Input
■ HDL Output
■ HIL (Hardware in the Loop)
■ Quartus II Global Project Assignment
■ Quartus II Pinout Assignments
■ Resource Usage
■ Signal Compiler
■ SignalTap II Logic Analyzer
■ SignalTap II Node
■ Simulation Accelerator
■ Subsystem Builder
■ TestBench
■ VCD Sink
1–2 Chapter 1: AltLab Library
BP (Bus Probe)
DSP Builder Reference Manual © March 2009 Altera Corporation
BP (Bus Probe)
The Bus Probe (BP) block is a sink, which can be placed on any node of a model. The
Bus Probe block does not have any hardware representation and therefore will not
appear in the VHDL RTL representation generated by the Signal Compiler block.
The Display in Symbol parameter selects the graphical shape of the symbol in your
model and the information that is reported there, as shown in Table 1–1.
After simulating your model, the Bus Probe block back-annotates the following
information in the parameters dialog box for the Bus Probe block:
■ Maximum value reached during simulation
■ Minimum value reached during simulation
■ Maximum number of integer bits required during simulation
Figure 1–1 shows example usage of the Bus Probe block. Max is displaying the
maximum value reached during simulation, Bits the maximum number of bits, and
Min the minimum value reached during simulation.
Clock
You can use the Clock block in the top level of your design to set the base hardware
clock domain.
The block name is used as the name of the clock signal and must be a valid VHDL
identifier.
There can be zero or one base clock in a design and an error is issued if you try to use
more than one base clock. You can choose the required units and enter any positive
value using the specified units. However, the clock period should be greater than 1ps
but less than 2.1ms.
If no base clock exists in your design, a default clock with a 20ns real-world period
and a Simulink sample time of 1 is automatically created.
Table 1–1. Bus Probe Block “Display in Symbol” Parameter
Shape of
Symbol Data Reported in Symbol
Circle Maximum number of integer bits required during simulation.
Rectangle Maximum or minimum value reached during simulation.
Figure 1–1. Bus Probe Block Example Usage
Chapter 1: AltLab Library 1–3
Clock_Derived
© March 2009 Altera Corporation DSP Builder Reference Manual
1 To avoid sample time conflicts in the Simulink simulation, ensure that the sample
time specified in the Simulink source block matches the sample time specified in the
Input block (driven by the Clock block or a derived clock).
Additional clocks can be placed in the system by adding Clock_Derived blocks.
Each clock must have a unique reset name. As all clock blocks have the same default
reset name (aclr) you must take care to specify a valid unique name when using
multiple clocks.
1 If you append _n to the specified reset name, the reset signal is negated irrespective of
the active level specified in the Clock block.
Table 1–2 lists the parameters for the Clock block:
Clock_Derived
You can use the Clock_Derived block in the top level of your design to add
additional clock pins to your design. These clocks must be specified as a rational
multiple of the base clock for simulation purposes.
The block name is used as the name of the clock signal and must be a valid VHDL
identifier.
You can specify the numerator and denominator multiplicands used to calculate the
derived clock. However, the resulting clock period should be greater than 1ps but less
than 2.1ms.
If no base clock is set in your design, a 20ns base clock is automatically created and
used to determine the derived clock period. You must use a Clock block to set the
base clock if you want the sample time to be anything other than 1.
1 To avoid sample time conflicts in the Simulink simulation, ensure that the sample
time specified in the Simulink source block matches the sample time specified in the
Input block (driven by the Clock block or a derived clock).
Each clock must have a unique reset name. As all clock blocks have the same default
reset name (aclr) you must take care to specify a valid unique name when using
multiple clocks.
Table 1–2. Clock Block Parameters
Name Value Description
Real-World Clock Period user specified Specify the clock period which should be greater than 1ps but less than
2.1 ms.
Period Unit ps, ns, us, ms, s Specify the units used for the clock period (picoseconds, nanoseconds,
microseconds, milliseconds, or seconds).
Simulink Sample Time > 0 Specify the Simulink sample time.
Reset Name User defined Specify a unique reset name. The default reset is aclr.
Reset Type Active Low,
Active High
Specify whether the reset signal is active high or active low.
Export As Output Pin On or Off Turn on to export this clock as an output pin.
1–4 Chapter 1: AltLab Library
Display Pipeline Depth
DSP Builder Reference Manual © March 2009 Altera Corporation
1 If you append _n to the specified reset name, the reset signal is negated irrespective of
the active level specified in the clock block.
Table 1–3 lists the parameters for the Clock_Derived block:
Display Pipeline Depth
The Display Pipeline Depth block controls whether to the pipeline depth is
displayed on primitive blocks.
You can change the display mode by double-clicking on the block. When set, the
current pipeline depth is displayed at the top right corner of each block that adds
latency to your design. The currently selected mode is shown on the Display
Pipeline Depth block symbol.
The Display Pipeline Depth block has no parameters.
HDL Entity
The HDL Entity block is used for black box simulation subsystems that are included
in your design using a Subsystem Builder block. The HDL Entity block specifies
the name of the HDL file that is substituted for the subsystem and the names of the
clock and reset ports for the subsystem.
This block is usually automatically created by the Subsystem Builder block.
Table 1–4 shows the parameters for the HDL Entity block.
Table 1–3. Clock_Derived Block Parameters
Name Value Description
Base Clock Multiplicand
Numerator
>= 1 Multiply the base clock period by this value. The resulting clock period should be
greater than 1ps but less than 2.1ms.
Base Clock Multiplicand
Denominator
>= 1 Divide the base clock period by this value. The resulting clock period should be
greater than 1ps but less than 2.1ms.
Reset Name User defined Specify a unique reset name. The default reset is aclr.
Reset Type Active Low,
Active High
Specify whether the reset signal is active high or active low.
Export As Output Pin On or Off Turn on to export this clock as an output pin.
Table 1–4. HDL Entity Block Parameters
Name Value Description
HDL File Name User defined Specifies the name of the HDL file that will be substituted for the subsystem
represented by a Subsystem Builder block.
Clock Name User defined Specifies the name of the clock signal used by the black box subsystem.
Reset Name User defined Specifies the name of the reset signal used by the black box subsystem.
HDL takes port names
from Subsystem
On or Off Turn on to use the subsystem port names as the entity port names instead of using
the names of the HDL Input and HDL Output blocks.
Chapter 1: AltLab Library 1–5
HDL Import
© March 2009 Altera Corporation DSP Builder Reference Manual
HDL Import
You can use the HDL Import block to import existing blocks implemented in HDL
into DSP Builder. The files can be individually specified VHDL or Verilog HDL files or
be defined in a Quartus
®
II project file.
1 Your model file must be saved before you can import HDL using the HDL Import
block.
When you click Compile, a simulation file is generated and the block in your model is
configured with the required input and output ports. The Quartus II software
synthesizes the imported HDL or project as a netlist of megafunctions, LPM functions,
and gates.
The megafunctions and LPM functions may have been explicitly instantiated in the
imported files, or may have been inferred by the Quartus II software. The netlist is
then compiled into a binary simulation netlist for use by the HDL simulation engine
in DSP Builder.
When simulating imported VHDL in ModelSim which includes FIFOs, there may be
Xs in the simulation results. This may give a mismatch with the Simulink simulation.
You should use the FIFO carefully to avoid any overflows or underflows. Examine
and eliminate any warnings of Xs reported by ModelSim during simulation before
you compare to the Simulink results.
The simulator supports many of the common megafunctions and LPM functions
although some are not supported. If an unsupported function is encountered, an error
message is issued after the compile button is clicked and the HDL cannot be
imported. However, you may be able to re-write the HDL so that the Quartus II
software infers a different megafunction or LPM function.
Table 1–5 shows the parameters for the HDL Import block.
Table 1–5. HDL Import Block Parameters (Part 1 of 2)
Name Value Description
Import HDL On or Off You can import individual HDL files when this option is on.
Add .v or .vhd file Click this button to browse for one or more VHDL files or Verilog HDL files.
Remove — Click this button to remove the selected file from the list.
Up, Down — Click these buttons to change the compilation order by moving the selected HDL file up
or down the list. The file order is not important when you are using the Quartus II
software but may be significant when you are using other downstream tools (such as
ModelSim).
Enter name of top
level design entity
Entity name Specifies the name of the top level entity in the imported HDL files.
Import Quartus II
Project
On or Off When this option is on, you can specify the HDL to import using a Quartus II project file
(.qpf). The current HDL configuration is imported. To import a different revision, the
required revision should be specified in the Quartus II software. The source files used
by the Quartus II project must be in the same directory as your model file or be
explicitly referenced in the Quartus II settings file (.qsf). Error messages are issued for
any entities which cannot be found. Refer to the Quartus II documentation for
information about setting the current revision of a project and how to explicitly
reference the source files in your design.
1–6 Chapter 1: AltLab Library
HDL Import
DSP Builder Reference Manual © March 2009 Altera Corporation
Figure 1–2 shows an example of an imported HDL design implementing a simple
adder with four input ports (Input, Input1, Input2, sclrp), and two output ports
(Output, Output1).
The input and output interfaces to the imported VHDL must be defined using
std_logic_1164 types. If your design uses any other VHDL type definitions (such as
arithmetic or numeric types), you should write a wrapper which converts them to
std_logic or std_logic_vector.
HDL import only supports single clock designs. If a design with multiple clocks is
imported, one clock is used as the implicit clock and any others are shown as input
ports on the Simulink block.
1 HDL source files can be stored in any directory or hierarchy of directories.
Table 1–6 lists the supported megafunctions and LPM functions.
Table 1–7 on page 1–7 lists the megafunctions and LPM functions that are not
supported.
Browse .qpf file Click this button to browse for a Quartus II project file.
Sort top-level
ports by name
On or Off Turn on to sort the ports defined in the top-level HDL file alphabetically instead of using
the order specified in the HDL.
Compile — This button compiles a simulation model from the imported HDL and displays the ports
defined in the imported HDL on the block.
Table 1–5. HDL Import Block Parameters (Part 2 of 2)
Figure 1–2. Typical HDL Import Block
Table 1–6. Supported Megafunctions and LPM Functions
Megafunctions LPM Functions
a_graycounter
altaccumulate
altmult_add
altshift_taps
altsyncram
parallel_add
scfifo
lpm_abs
lpm_add_sub
lpm_compare
lpm_counter
lpm_mult (Note 1)
lpm_mux
lpm_ram_dp
Note to Table 1–6:
(1) The lpm_mult LPM function is not supported when configured to perform a squaring operation.
Chapter 1: AltLab Library 1–7
HDL Input
© March 2009 Altera Corporation DSP Builder Reference Manual
HDL Input
The HDL Input block should be connected directly to an input node in a subsystem.
It is intended for use with a HDL Entity block for black box simulation.
The type and bit width specified for the HDL Input block should match the type and
bit width on the corresponding input port in the HDL file referenced in the HDL
Entity block. This block is usually automatically generated by the Subsystem
Builder block.
You can optionally specify the external Simulink type. If set to Simulink Fixed
Point Type, the bit width is the same as the input. If set to Double, the width may
be truncated if the bit width is greater than 52.
Table 1–8 shows the HDL Input block parameters.
.
Table 1–9 on page 1–8 shows the HDL Input block I/O formats.
Table 1–7. Unsupported Megafunctions and LPM Functions
Megafunctions LPM Functions
alt3pram
altcam
altcdr
altclklock
altddio
altdpram
altera_mf_common
altfp_mult
altlvds
altmemmult
altmult_accum
altpll
altqpram
altsqrt
alt_exc_dpram
alt_exc_upcore
dcfifo
lpm_and
lpm_bustri
lpm_clshift
lpm_constant
lpm_decode
lpm_divide
lpm_ff
lpm_fifo
lpm_fifo_dc
lpm_inv
lpm_latch
lpm_or
lpm_pad
lpm_ram_dq
lpm_ram_io
lpm_rom
lpm_shiftreg
lpm_xor
Table 1–8. HDL Input Block Parameters
Name Value Description
Bus Type Signed Integer,
Signed Fractional,
Unsigned Integer,
Single Bit
Choose the number format of the bus.
[number of bits].[] >= 0
(Parameterizable)
Specify the number of bits to the left of the binary point, including the
sign bit. This parameter does not apply to single-bit buses.
[].[number of bits] >= 0
(Parameterizable)
Specify the number of bits to the right of the binary point. This parameter
applies only to signed fractional buses.
External Type Inferred,
Simulink Fixed Point Type,
Double
Specifies whether the external type is inferred from the Simulink block it
is connected to or explicitly set to either Simulink Fixed Point or Double
type. The default is Inferred.
1–8 Chapter 1: AltLab Library
HDL Output
DSP Builder Reference Manual © March 2009 Altera Corporation
HDL Output
The HDL Output block should be connected directly to an output node in a
subsystem. It is intended to be used with the HDL Entity block for black box
simulation.
The type and bit width specified for the HDL Output block should match the type
and bit width on the corresponding output port in the HDL file referenced in the HDL
Entity block. This block is usually automatically generated by the Subsystem
Builder block.
Table 1–10 shows the HDL Output block parameters.
Table 1–11 shows the HDL Output block I/O formats.
Table 1–9. HDL Input Block I/O Formats (Note 1)
I/O Simulink (2), (3) VHDL Type (4)
II1
[L1].[R1]
I1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) Implicit - Optional
OO1
[LP].[RP]
O1: out STD_LOGIC_VECTOR({LP + RP - 1} DOWNTO 0) Explicit
Notes to Table 1–9:
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
(3) I1
[L].[R]
is an input port. O1
[L].[R]
is an output port.
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the data path
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
Table 1–10. HDL Output Block Parameters
Name Value Description
Bus Type Signed Integer,
Signed Fractional,
Unsigned Integer,
Single Bit
Choose the number format of the bus.
[number of bits].[] >= 0
(Parameterizable)
Specify the number of bits to the left of the binary point, including the sign bit.
This parameter does not apply to single-bit buses.
[].[number of bits] >= 0
(Parameterizable)
Specify the number of bits to the right of the binary point. This parameter applies
only to signed fractional buses.
Table 1–11. HDL Output Block I/O Formats (Note 1)
I/O Simulink (2), (3) VHDL Type (4)
II1
[L1].[R1]
I1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) Implicit - Optional
OO1
[LP].[RP]
O1: out STD_LOGIC_VECTOR({LP + RP - 1} DOWNTO 0) Explicit
Notes to Table 1–11:
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
(3) I1
[L].[R]
is an input port. O1
[L].[R]
is an output port.
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the data path
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.

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